This article describes a highly parallel event driven interface between a Pixel Array Detector (PAD) and its processing electronics. The method used was originally developed for the Field Programmable Gate Array (FPGA) X-ray Pixel Array detector to allow for real-time processing of X-ray image data on its processing FPGA. This interface potentially allows for entirely asynchronous data transfer off the detector at rates exceeding 110Gbps and operates without the need for a constantly running clock. It thus presents a potential a low-power, low-noise interface option for 10-bit data transfer from photon-counting detectors at frame rates greater than 1MHz with no input dead time. This interface has been successfully tested on 64 independent 16-pixel channels at a transfer frequency of 294MHz achieving maximum data transfer rates of 16.7 Gbps. © 2019 IEEE.